Semiconductor device, method of manufacturing the same and power conversion device

ABSTRACT

A semiconductor device includes a semiconductor chip, a cell surface electrode portion, and a peripheral edge surface structure portion. The semiconductor chip has a cell portion and a peripheral edge portion provided around the cell portion in plan view. The cell surface electrode portion is provided on the cell portion. The peripheral edge surface structure portion is provided on the peripheral edge portion. The peripheral edge portion is made thinner than the cell portion so that a back surface of the peripheral edge portion is more concave than a back surface of the cell portion. When the thickness of the cell portion is represented by tc and the size of the step between the cell portion and the peripheral edge portion on the back surface is represented by dtb, 0%&lt;dtb/tc≤1.5% is satisfied.

FIELD

The present invention relates to a semiconductor device, a method ofmanufacturing the same and a power conversion device.

BACKGROUND

For example, as disclosed in JP 2009-71044 A, a semiconductor devicehaving a convex portion provided on a surface of a semiconductor layerhas been conventionally known. The semiconductor device described inparagraph [0016], FIG. 1, etc. of the above publication includes asemiconductor layer, an emitter electrode formed on the surface of thesemiconductor layer, a first convex portion provided along the outerperiphery of the surface of the semiconductor device so as to make around inside the periphery, and a second convex portion formed in aninner range of the first convex portion.

Patent Literature 1: JP 2009-71044 A

SUMMARY

A semiconductor chip constituting the semiconductor device includes acell portion having a semiconductor active element formed therein, and aperipheral edge portion provided on the periphery of the cell portion. Acell surface electrode portion is provided on the cell portion, and aperipheral edge surface structure portion is provided on the peripheraledge portion. The cell surface electrode portion and the peripheral edgesurface structure portion have different heights in some cases. In thiscase, a step exists on the surface of a semiconductor wafer beforeformation of a chip.

In order to reduce the thickness of the semiconductor wafer, a step ofgrinding the back surface of the semiconductor wafer is frequentlyexecuted. When the back surface grinding step is executed, a leveldifference corresponding to the size of a step on the front surface ofthe semiconductor wafer is formed on the back surface of the wafer. Whenthe peripheral edge surface structure portion is provided to be higherthan the cell surface electrode portion, the back surface of theperipheral edge portion is ground more deeply than the back surface ofthe cell portion by the back surface grinding step. As a result, a backsurface of the peripheral edge portion is more concave than a backsurface of the cell portion. One characteristic of semiconductor devicesfor power is a reverse bias safe operation area (RBSOA). When the leveldifference on the back surface between the peripheral edge portion andthe cell portion is too large, it causes a problem that currentconcentration occurring in the cell portion reduces RBSOA resistance.

The present application has an object to provide a semiconductor devicethat is improved so as to be capable of suppressing currentconcentration on a cell portion, a manufacturing method thereof, and apower conversion device.

A semiconductor device according to a first aspect of the presentapplication includes: a semiconductor chip, a cell surface electrodeportion, and a peripheral edge surface structure portion. Thesemiconductor chip has a plane-body shape having a front surface and aback surface. The semiconductor chip includes a cell portion provided ina central region in plan view of the plane-body shape and a peripheraledge portion provided around the cell portion in the plan view of theplane-body shape. The cell surface electrode portion is provided on thefront surface of the cell portion. The peripheral edge surface structureportion is provided on the front surface of the peripheral edge portion,and has a top surface higher than a top surface of the cell surfaceelectrode portion. The peripheral edge portion is made thinner than thecell portion so that the back surface of the peripheral edge portion ismore concave than the back surface of the cell portion. When a thicknessof the cell portion is represented by to and a level difference betweenthe cell portion and the peripheral edge portion on the back surface isrepresented by dtb, 0%<dtb/tc≤1.5% is satisfied.

A power conversion device according to a second aspect of the presentapplication includes: a main conversion circuit that includes asemiconductor device, converts input power by the semiconductor deviceand outputs the converted input power, a driving circuit for outputtinga drive signal for driving the semiconductor device to the semiconductordevice; and a control circuit for outputting a control signal forcontrolling the driving circuit to the driving circuit. Thesemiconductor device includes a semiconductor chip, a cell surfaceelectrode portion, and a peripheral edge surface structure portion. Thesemiconductor chip has a plane-body shape having a front surface and aback surface. The semiconductor chip includes a cell portion provided ina central region in plan view of the plane-body shape, and a peripheraledge portion provided around the cell portion in the plan view of theplane-body shape. The cell surface electrode portion is provided on thefront surface of the cell portion. The peripheral edge surface structureportion is provided on the front surface of the peripheral edge portion,and has a top surface higher than a top surface of the cell surfaceelectrode portion. The peripheral edge portion is made thinner than thecell portion so that the back surface of the peripheral edge portion ismore concave than the beck surface of the cell portion. When a thicknessof the cell portion is represented by tc and a level difference betweenthe cell portion and the peripheral edge portion on the back surface isrepresented by dtb, 0%<dtb/tc≤1.5% is satisfied.

A semiconductor device manufacturing method according to a third aspectof the present application includes: a preparing step, an elementforming step, a surface structure forming step, a back surface grindingstep, and a dicing step. In the preparing step, a semiconductor waferhaving a front surface and a back surface is prepared. In the elementforming step, a semiconductor active element is formed in a cell portionas a predetermined part in the semiconductor wafer. In the surfacestructure forming step, a cell surface electrode portion is formed on afront surface of the cell portion after the semiconductor active elementis formed, and a peripheral edge surface structure portion is formed ina peripheral edge portion around the cell portion on the front surfaceof the semiconductor wafer so that the peripheral edge surface structurehas a top surface higher than a top surface of the cell surfaceelectrode portion. The cell surface electrode portion and the peripheraledge surface structure portion are formed so that 0%<dtf/tc≤1.5% issatisfied when a thickness of the cell portion is represented by tc anda difference in height between the top surface of the cell surfaceelectrode portion and the top surface of the peripheral edge surfacestructure portion is represented by dtf. In the back surface grindingstep, wafer thinning of grinding the back surface of the semiconductorwafer is performed after the cell surface electrode portion and theperipheral edge surface structure portion are formed, whereby a leveldifference occurring on the front surface due to the cell surfaceelectrode portion and the peripheral edge surface structure portion istransferred onto the back surface of the peripheral edge portion. In thedicing step, dicing of the semiconductor wafer along a dicing lineprovided on an outer periphery of the peripheral edge portion isconducted after performing the wafer thinning.

Other and further objects, features and advantages of the invention willappear more fully from the following description.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a plan view showing a structure of a semiconductor deviceaccording to a first embodiment;

FIG. 2 is a cross-sectional view showing the structure of thesemiconductor device according to the first embodiment;

FIG. 3 is a graph showing the action and effect of the semiconductordevice according to the first embodiment;

FIG. 4 is a graph showing the action and effect of the semiconductordevice according to the first embodiment;

FIG. 5 is a diagram showing the action and effect of the semiconductordevice of the first embodiment by using a comparative example to theembodiment;

FIG. 6 is a diagram showing the action and effect of the semiconductordevice of the first embodiment by using a comparative example to theembodiment;

FIG. 7 is a graph showing the action and effect of the semiconductordevice according to the first embodiment;

FIG. 8 is a cross-sectional view showing a structure of a semiconductordevice according to a modification of the first embodiment;

FIG. 9 is a cross-sectional view showing a structure of a semiconductordevice according to a second embodiment;

FIG. 10 is a cross-sectional view showing a structure of a semiconductordevice according to a third embodiment;

FIG. 11 is a cross-sectional view showing a structure of a semiconductordevice according to a fourth embodiment;

FIG. 12 is a cross-sectional view showing the structure after thesemiconductor device according to the fourth embodiment is mounted;

FIG. 13 is a diagram showing comparative examples relating to thepresent embodiment;

FIG. 14 is a diagram showing comparative examples relating to thepresent embodiment;

FIG. 15 is a cross-sectional view showing a structure of a semiconductordevice according to a fifth embodiment;

FIG. 16 is a cross-sectional view showing a structure of a semiconductordevice according to a sixth embodiment;

FIG. 17 is a flowchart showing a method of manufacturing a semiconductordevice according to a seventh embodiment;

FIG. 18 is a flowchart showing a method of manufacturing a semiconductordevice according to a eighth embodiment; and

FIG. 19 is a block diagram showing a power conversion device accordingto a ninth embodiment.

DESCRIPTION OF EMBODIMENTS

FIG. 1 is a plan view showing a structure of a semiconductor device 100according to a first embodiment. The semiconductor device 100 includes asemiconductor chip 20, a cell surface electrode portion 30, a peripheraledge surface structure portion 32, and a gate pad 34. The semiconductorchip 20 has a plane-body shape having a front surface and a backsurface.

The semiconductor chip 20 includes a cell portion 21, a peripheral edgeportion 22, and a dicing line portion 23. The cell portion 21 is a partof a central region of the semiconductor chip 20 in plan view. The cellportion 21 is provided with a semiconductor active element. In the firstembodiment, specifically, the cell portion 21 is provided with atransistor element, and more specifically, this transistor element is aninsulated gate bipolar transistor (IGBT). The peripheral edge portion 22is a square annular part provided around the cell portion 21 in planview of the semiconductor chip 20. The dicing line portion 23 is asquare annular part provided on the outer periphery of the peripheraledge portion 22 in plan view of the semiconductor chip 20.

The cell surface electrode portion 30 is provided on the cell portion21. The peripheral edge surface structure portion 32 is provided on theperipheral edge portion 22. As shown in the cross-sectional view of FIG.2, the top surface of the peripheral edge surface structure portion 32is higher than the top surface of the cell surface electrode portion 30.

FIG. 2 is a cross-sectional view showing the structure of thesemiconductor device 100 according to the first embodiment. FIG. 2 showsa cross-section of the semiconductor device 100 taken along line A-A′ inFIG. 1. In FIG. 2, the cell portion 21, the peripheral edge portion 22and the dicing line portion 23 in the semiconductor chip 20 aredemarcated from one another by broken lines. The peripheral edge portion22 is further demarcated into a gate wiring portion 22 a providedadjacently to the cell portion 21 and a peripheral edge concave portion22 b provided outside the gate wiring portion 22 a.

The semiconductor chip 20 has an n-type semiconductor substrate 1. Inthe first embodiment, it is assumed that the material of thesemiconductor substrate 1 is silicon. As a modification, the material ofthe semiconductor substrate 1 may be a wide bandgap semiconductor havinga larger bandgap than silicon. SiC, GaN or diamond may be used as thewide bandgap semiconductor.

In the semiconductor device 100 according to the first embodiment, thecell portion 21 is provided with an insulated gate bipolar transistor(IGBT). However, instead of the IGBT, another transistor element such asa field effect transistor (MOSFET) may be provided to the cell portion21. For example, when the semiconductor substrate 1 is modified fromsilicon to SiC, the transistor element formed in the cell portion 21 maybe MOSFET. In addition, the cell portion 21 may be provided with anothersemiconductor active element such as a diode element instead of thetransistor element. The modifications applied to the material of thesemiconductor substrate 1 and the semiconductor active element describedhere can be likewise applied to all the embodiments described later.

In the semiconductor chip 20, semiconductor active elements are formedon the front surface and the back surface of the semiconductor substrate1 by element formation processes such as impurity implantation andetching. A p-type base layer 3 is provided over the cell portion 21 andthe peripheral edge portion 22 on a front-surface side of thesemiconductor chip 20. On the front-surface side of the semiconductorchip 20, the cell portion 21 is provided with plural trench gates 2penetrating through the base layer 3 and reaching the semiconductorsubstrate 1, plural emitter layers 4 of n⁺-type each provided on bothsides of each of the trench gates 2, and plural diffusion layers 5 ofp⁺-type provided between the plural emitter layers 4.

On a back-surface side of the semiconductor chip 20, an n-type firstbuffer layer 12, an n-type second buffer layer 13, and a collector layer14 are provided over the whole area of the cell portion 21, theperipheral edge portion 22 and the dicing line portion 23. The collectorlayer 14, the second buffer layer 13, and the first buffer layer 12 arestacked in turn from the backmost side of the semiconductor chip 20. Thefirst buffer layer 12 is formed by performing impurity implantation orirradiation on a deep portion of the back surface of the semiconductorsubstrate 1. The second buffer layer 13 is formed by performing impurityimplantation only on a shallow portion of the back surface of thesemiconductor substrate 1.

The cell surface electrode portion 30 is provided on the cell portion 21of the semiconductor chip 20. The cell surface electrode portion 30includes an interlayer insulating film 7 stacked on the front surface ofthe semiconductor chip 20, plural contact portions 6 formed ofconductors penetrating through the interlayer insulating film 7, and afirst emitter electrode 8 which is provided on the interlayer insulatingfilm 7 and connected to the contact portions 6. The first emitterelectrode 8 is formed of a material having a low resistance such as ametal.

On the back surface of the semiconductor chip 20, a collector electrode15 is provided over the whole area of the cell portion 21, theperipheral edge portion 22, and the dicing line portion 23. Thesestructures provided on the front surface and the back surface form IGBTin the cell portion 21.

The peripheral edge surface structure portion 32 is provided on theperipheral edge portion 22 of the semiconductor chip 20. The peripheraledge surface structure portion 32 includes the interlayer insulatingfilm 7, plural first field plate electrodes 9, an upper layer insulatingfilm 37, plural second field plate electrodes 10, and a protectiveinsulating film 11. The interlayer insulating film 7 is stacked on thesurface of the peripheral edge portion 22 of the semiconductor chip 20.The plural first field plate electrodes 9 are provided on the interlayerinsulating film 7 while being spaced apart from one another. The firstfield plate electrodes 9 may be formed of an n-type polysilicon film.The upper layer insulating film 37 covers the plural first field plateelectrodes 9. The plural second field plate electrodes 10 are providedon the upper layer insulating film 37 while being spaced apart from oneanother. Like the first emitter electrode 8, the second field plateelectrodes 10 may be formed of a material having a low resistance suchas a metal.

The protective insulating film 11 covers the plural second field plateelectrodes 10. The protective insulating film 11 is an uppermost layerof the peripheral edge surface structure portion 32, and covers thefirst field plate electrodes 9, the upper layer insulating film 37 andthe second field plate electrodes 10. The protective insulating film 11is a structure provided for the purpose of securing a withstand voltageand reliability, and is formed only in the peripheral edge portion 22 inthe first embodiment. An end portion 11 a of the protective insulatingfilm 11 covers parts of an end face and an upper face of the firstemitter electrode 8.

A contact portion 36 penetrating through the upper layer insulating film37 is formed in the gate wiring portion 22 a out of the peripheral edgeportion 22. The contact portion 36 connects the first field plateelectrode 9 and the second field plate electrode 10.

When the semiconductor device 100 according to the first embodiment isviewed as a simple product substance, no other structure is provided onthe first emitter electrode 8, and the first emitter electrode 8 is keptin an exposed state. When the semiconductor device 100 is mounted in acase or the like to construct a power conversion device or the like,wires and solder are formed on the first emitter electrode 8.

The height of the top surface of the cell surface electrode portion 30and the height of the top surface of the peripheral edge surfacestructure portion 32 in the semiconductor device 100 are respectivelydefined. “The height of the top surface of the cell surface electrodeportion 30” is defined as the height from the surface of thesemiconductor chip 20 in the cell portion 21 to the upper surface of thefirst emitter electrode 8. “The height of the top surface of the cellsurface electrode portion 30” is equal to the sum of the thickness ofthe interlayer insulating film 7 and the thickness of the first emitterelectrode 8.

“The height of the top surface of the peripheral edge surface structureportion 32” is defined as the height from the surface of thesemiconductor chip 20 in the peripheral edge portion 22 to the uppersurface of the protective insulating film 11. “The height of the topsurface of the peripheral edge surface structure portion 32” is equal tothe sum of the thickness of the interlayer insulating film 7, thethickness of the upper layer insulating film 37 covering the first fieldplate electrodes 9, and the thickness of the protective insulating film11 covering the second field plate electrodes 10. The top surface of theperipheral edge surface structure portion 32 is higher than the topsurface of the cell surface electrode portion 30, and a level differencecaused by the difference in height between these top surfaces isreferred to as “front-surface level difference dtf”.

The interlayer insulating film 7 is provided on the surface of thesemiconductor chip 20 in the dicing line portion 23. The top surface ofthe dicing line portion 23 is lower than the top surface of theperipheral edge surface structure portion 32, and a level differencecaused by the difference in height between these top surfaces isreferred to as “end portion front-surface level difference dtdf”.

As shown in FIG. 2, a step is provided on the back surface side of thesemiconductor device 100. That is, the semiconductor chip 20 has astructure in which the peripheral edge portion 22 is made thinner thanthe cell portion 21 so that the back surface of the peripheral edgeportion 22 is more concave than the back surface of the cell portion 21.The back surface of the cell portion 21 is shaped to be flat in parallelto the front surface of the cell portion 21. The peripheral edge portion22 has different back surface structures in the gate wiring portion 22 aand the peripheral edge concave portion 22 b. The back surface of thegate wiring portion 22 a has a tapered shape so as to be inclined withrespect to the surface of the gate wiring portion 22 a. The back surfaceof the peripheral edge concave portion 22 b is shaped to be flat inparallel to the front surface of the peripheral edge concave portion 22b.

As shown in FIG. 2, the thickness of the cell portion 21 is representedby tc. More specifically, the thickness to is the thickness of the cellportion 21 at the boundary between the cell portion 21 and theperipheral edge portion 22. As shown in FIG. 2, the minimum thickness ofthe peripheral edge portion 22 is represented by tp. More specifically,the minimum thickness tp is the thickness of the peripheral edge concaveportion 22 b which is the thinnest portion of the peripheral edgeportion 22. The size of the step between the cell portion 21 and theperipheral edge portion 22 on the back surface is referred to as a firstback-surface level difference dtb. The first back-surface leveldifference dtb is equal to the difference between the thickness to andthe minimum thickness tp.

In the first embodiment, the peripheral edge portion 22 is made thinnerthan the cell portion 21 within a range satisfying the followingexpression (1). In the following expression (1), it is assumed thatdtb≠0 and tc≠0.0%<dtb/tc≤1.5%  (1)

A level difference corresponding to the dimension of the step betweenthe cell surface electrode portion 30 and the peripheral edge surfacestructure portion 32 is transferred onto the back surface of thesemiconductor wafer by the grinding step of the back surface of thesemiconductor wafer to reduce the wafer thickness. Details of thisgrinding step will be described with reference to a manufacturing methodaccording to a seventh embodiment to be described later. It is generalthat the transfer of the level difference described above makes thefront-surface level difference dtf and the first back-surface leveldifference dtb equal to each other.

In order to obtain the first back-surface level difference dtbsatisfying the foregoing expression (1) after the grinding step of theback surface of the semiconductor wafer, it is preferable that thefront-surface level difference dtf satisfies the following expression(2) in the first embodiment. In the following expression (2), it isassumed that dtf≠0 and tc≠0.0%<dtf/tc≤1.5%  (2)

As shown in FIG. 2, in the first embodiment, the dicing line portion 23is made thicker than the peripheral edge portion 22 so that the backsurface of the dicing line portion 23 protrudes as compared with theback surface of the peripheral edge portion 22. As shown in FIG. 2, thethickness of the dicing line portion 23 is represented by td. The sizeof the step between the dicing line portion 23 and the peripheral edgeportion 22 on the back surface of the semiconductor chip 20 is referredto as “second back-surface level difference dtp”. The secondback-surface level difference dtp is equal to the difference between thethickness td and the minimum thickness tp.

In the first embodiment, the dicing line portion 23 is made thicker thanthe peripheral edge portion 22 within a range satisfying the followingexpression (3). In the following expression (3), it is assumed thatdtp≠0 and td≠0.1.5%≤dtp/td  (3)

FIGS. 3 and 4 are graphs showing the action and effect of thesemiconductor device 100 according to the first embodiment. FIG. 3 showsthe difference in RBSOA test results according to the value of dtb/tcwhich is the ratio between the first back-surface level difference dtband the thickness tc of the cell portion 21. RBSOA represents anabbreviation of Reverse Bias Safe Operation Area.

The graph of FIG. 3 shows a simulation result of a current densitydistribution at a B-B′ cross-sectional portion of FIG. 2 under the RBSOAtest. A circuit used for the test is a switching circuit for a generalRBSOA test. The test condition is that the junction portion temperatureTj=448 K, the collector-emitter voltage Vce=800 V, the gate-emittervoltage Vge=20 V/−15 V, the collector current Ic=1150 A, and theparasitic inductance L=70 nH. FIG. 3 shows a solid-line graph in whichdtb/tc is equal to 1.5% or less and a broken-line graph in which dtb/tcis larger than 1.5%. In the broken-line graph in which dtb/tc is largerthan 1.5%, current concentrates on the cell portion 21, so that theRBSOA resistance has deteriorated.

FIG. 4 shows the dtb-dependence of a breakable current of RBSOA. Whenthe value of dtb/tc is larger than 1.5%, the breakable current decreasesaccording to the increase of dtb/tc. For example, when the firstback-surface level difference dtb is so large that the value of dtb/tcreaches 2.0%, the breakable current decreases to about one third. Suchdecrease of RBSOA resistance is not preferable

When the thickness tc of the semiconductor wafer is sufficiently large,the influence of the first back-surface level difference dtb isinsignificant. However, as the thickness tc decreases due to thinning ofthe semiconductor wafer, the rate of the first back-surface leveldifference dtb to the thickness tc increases. Therefore, in recenttechnical trends in which thinning of semiconductor wafers has beenpursued, there is a problem that the problem of decrease of RBSOAresistance due to the first back-surface level difference dtb becomesobvious.

In this regard, according to the first embodiment, the firstback-surface level difference dtb is adjusted within the range of theabove-described expression (2). Since the first back-surface leveldifference dtb can be kept within a certain range so that the peripheraledge portion 22 is not excessively thin as compared with the cellportion 21, the value of dtb/tc is suppressed to 1.5% or less. As aresult, as shown in FIG. 4, the first back-surface level difference dtbcan be managed within a range that does not cause decrease of the RBSOAbreakable current. In particular, according to data shown in FIG. 4, bysetting the value of dtb/tc to 1.5% or less, RBSOA controllable Ic canbe secured to be seven times or more as large as rated Ic.

FIGS. 5 and 6 are diagrams showing the action and effect of thesemiconductor device 100 of the first embodiment by using a comparativeexample to the embodiment. As the first back-surface level differencedtb becomes larger, the minimum thickness tp of the peripheral edgeportion 22 becomes smaller. FIG. 5 is a graph represented as acomparative example, and shows a current density distribution of thesemiconductor device 100 when it is assumed that dtb=0, that is, thereis no back-surface level difference. FIG. 6 is a graph represented as acomparative example, and shows a current density distribution of thesemiconductor device 100 when it is assumed that dtb/tc>1.5%. Sincethere is a difference in the presence or absence of the back-surfacelevel difference, the minimum thickness tp of the peripheral edgeportion 22 in FIG. 6 is thinner than that in FIG. 5.

When comparing FIGS. 5 and 6 with each other, a depletion layer end Q isprone to reach the back surface of the semiconductor chip 20 in a resultof FIG. 6 where the minimum thickness tp of the peripheral edge portion22 is smaller. When the depletion layer end Q tends to reach the backsurface of the semiconductor chip 20, holes accumulated in theperipheral edge portion 22 are prone to flow into the cell portion 21.The flow of the accumulated holes of the peripheral edge portion 22 intothe cell portion 21 causes current concentration on the cell portion 21.

FIG. 7 is a graph showing the action and effect of the semiconductordevice 100 according to the first embodiment. The graph of FIG. 7 showsa simulation result of a hole density distribution at the B-B′cross-sectional portion of FIG. 2. A solid-line graph of dtb/tc≤1.5% anda broken-line graph of dtb/tc>1.5% are shown in FIG. 7. The hole densityof the cell portion 21 increases more greatly in the broken-line graphthan that in the solid-line graph. The result shown in FIG. 7 indicatesthat when the first back-surface level difference dtb is large, currentconcentration on the cell portion 21 occurs, as understood from thecomparison result between FIGS. 5 and 6 described above.

In this regard, according to the first embodiment, the relationship inthickness between the cell portion 21 and the peripheral edge portion 22can be kept within a certain range so that the peripheral edge portion22 is not excessively thinned as compared with the cell portion 21. Whenthe peripheral edge portion 22 is suppressed from being excessivelythinned as compared with the cell portion 21, the distance between thedepletion layer end Q in the peripheral edge portion 22 and the backsurface of the peripheral edge portion 22 can be suppressed from beingexcessively short. Since the distance between the depletion layer end Qin the peripheral edge portion 22 and the back surface of the peripheraledge portion 22 can be secured to be large to some extent, the holesaccumulated in the peripheral edge portion 22 can be prevented fromflowing into the cell portion 21. By suppressing the holes accumulatedin the peripheral edge portion 22 from flowing into the cell portion 21,it is possible to suppress occurrence of increase in hole density in thecell portion 21. Suppression of the increase in hole density in the cellportion 21 makes it possible to suppress current concentration on thecell portion 21. By suppressing the current concentration on the cellportion 21, it is possible to suppress decrease in RBSOA resistance.

In the first embodiment, since the protective insulating film 11 coversthe edge portion of the first emitter electrode 8, that is, the edgeportion of the cell surface electrode portion 30, the following effectis obtained. When the end portion of the first emitter electrode 8 andthe end portion of the protective insulating film 11 are flush with eachother, there is a risk that a gap may be formed between the firstemitter electrode 8 and the protective insulating film 11 due tomanufacturing variations. When the surface of the semiconductor chip 20is exposed by this gap, moisture may infiltrate from the exposed part ofthe gap. In this respect, according to the first embodiment, theoccurrence of the gap as described above can be prevented by coveringthe side end face and the upper-surface edge portion of the firstemitter electrode 8 with the protective insulating film 11. Therefore,the infiltration of moisture can be suppressed, and the reliability ofthe semiconductor device 100 can be enhanced.

Further, according to the first embodiment, the following effect can beobtained by satisfying the condition of the above-described expression(3) with reference to the dicing line portion 23. In order to reducewearing of a dicing blade, it is preferable that no film is provided onthe dicing line portion 23 or the film thickness is reduced to be assmall as possible even when a film is provided on the dicing lineportion 23. When the end portion front-surface level difference dtdf islarge, the end portion front-surface level difference dtdf istransferred onto the back surface of the wafer by grinding of the backsurface of the wafer. As a result of the transfer, the secondback-surface level difference dtp has a certain degree of magnitude.However, the dicing line portion 23 does not serve as a current pathduring the RBSOA operation. Accordingly, even when a large leveldifference is transferred onto the back surface so that dtp/td is equalto 1.5% or more, the RBSOA resistance does not deteriorate. According tothe first embodiment, the wearing of the dicing blade can be reducedwithout reducing the RBSOA resistance by making dtp/td to be 1.5% ormore.

FIG. 8 is a cross-sectional view showing a structure of a semiconductordevice 110 according to a modification of the first embodiment. In thesemiconductor device 110 according to the modification, the uppersurface of the first emitter electrode 8 is set to be higher than theupper surfaces of the second field plate electrodes 10. The differencein height between these upper surfaces is referred to as “dimension dte”of FIG. 8”.

According to the structure shown in FIG. 8, since the upper surfaces ofthe second field plate electrodes 10 are lower than the upper surface ofthe first emitter electrode 8, the protective insulating film 11 cansufficiently cover the second field plate electrodes 10 even when theprotective insulating film 11 is made thin to the extent that theprotective insulating film 11 slightly covers the upper surface of thefirst emitter electrode 8. Since the protective insulating film 11 canbe adjusted to have any arbitrary thickness without losing the coatingperformance of the second field plate electrodes 10, it is easy toadjust the front-surface level difference dtf between the upper surfaceof the first emitter electrode 8 and the upper surface of the protectiveinsulating film 11. When it becomes easier to adjust the front-surfacelevel difference dtf, it also becomes easier to adjust the firstback-surface level difference dtb to be transferred to the back surface.As a result, there is an advantage that the adjustment of dtb/tc tosatisfy the above expression (1) becomes easy.

The first back-surface level difference dtb restricted by the foregoingexpression (1) and the second back-surface level difference dtprestricted by the foregoing expression (3) may be set independently ofeach other. In the first embodiment, since dtdf is suppressed forsuppression of wearing of the dicing blade, the relationship of dtf<dtdfis satisfied. Therefore, it is estimated that dtb<dtp is satisfied.However, the magnitude relationship between dtb and dtp is not limited.Both of dtb and dtp may be different in magnitude while any one of dtband dtp is larger than the other, or both of them may be identical toeach other in magnitude.

Second Embodiment

FIG. 9 is a cross-sectional view showing a structure of a semiconductordevice 120 according to a second embodiment. The semiconductor device120 is different from the semiconductor device 100 according to thefirst embodiment in that a second emitter electrode 16 is provided inaddition to the first emitter electrode 8. Other configurations are thesame as those in the first embodiment. The second emitter electrode 16is stacked on the first emitter electrode 8, and is formed of a materialhaving a lower thermal resistance than that of the first emitterelectrode 8. The material of the second emitter electrode 16 may be Cuor the like.

In the second embodiment, the upper surface of the second emitterelectrode 16 serves as the top surface of the cell surface electrodeportion 30. In the second embodiment, a front-surface level differencedtf is provided so as to satisfy the condition of the expression (2)described with reference to the first embodiment. By providing thesecond emitter electrode 16 having a low thermal resistance, the heatdissipation is enhanced, so that SCSOA resistance can be enhanced. SCSOAis an abbreviation for “Short Circuit Safe Operation Area”.

The second embodiment may be modified so that the upper surfaces of thesecond field plate electrodes 10 may be higher than the upper surface ofthe second emitter electrode 16. In addition, the various modificationsdescribed with reference to the first embodiment may be applied to thesecond embodiment.

Third Embodiment

FIG. 10 is a cross-sectional view showing a structure of a semiconductordevice 130 according to a third embodiment. The semiconductor device 130is different from the semiconductor device 100 according to the firstembodiment in that the interlayer insulating film 7 in the cell portion21 is replaced by an interlayer insulating film 17. Other configurationsare the same as those in the first embodiment. The cell surfaceelectrode portion 30 includes the interlayer insulating film 17, and thecontact portion 6 is provided to the interlayer insulating film 17. Theperipheral edge surface structure portion 32 includes the interlayerinsulating film 7 and the upper layer insulating film 37 as in the caseof the first embodiment, and is provided with the contact portion 36penetrating through the upper layer insulating film 37.

For convenience of description, in the semiconductor device 130, thecontact portion 6 is also referred to as “cell contact portion 6”, thecontact portion 36 is also referred to as “peripheral edge contactportion 36”, the interlayer insulating film 17 is also referred to as“cell portion interlayer insulating film 17”, and the upper layerinsulating film 37 of the peripheral edge portion 22 is also referred toas “peripheral edge portion insulating film 37”. In the thirdembodiment, the cell portion interlayer insulating film 17 is madethicker than the peripheral edge portion insulating film 37. A parasiticcapacitance is generated by the first emitter electrode 8, thesemiconductor substrate 1 and the interlayer insulating film sandwichedbetween the first emitter electrode 8 and the semiconductor substrate 1.The parasitic capacitance can be reduced by replacing the interlayerinsulating film 7 of the cell portion 21 according to the firstembodiment with the cell portion interlayer insulating film 17 having alarge thickness according to the third embodiment.

The third embodiment may be modified so that the upper surfaces of thesecond field plate electrodes 10 are higher than the upper surface ofthe first emitter electrode 8. In addition, the various modificationsdescribed with reference to the first embodiment may be applied to thethird embodiment. Furthermore, the third embodiment may be modified sothat the cell surface electrode portion 30 includes the first emitterelectrode 8 and the second emitter electrode 16 as in the case of thesecond embodiment.

Fourth Embodiment

FIG. 11 is a cross-sectional view showing a structure of a semiconductordevice 140 according to a fourth embodiment. FIG. 12 is across-sectional view showing the structure after the semiconductordevice 140 according to the fourth embodiment is mounted. As shown inFIG. 12, after the semiconductor device 140 is mounted, a scalingmaterial 50 is provided on the peripheral edge surface structure portion32. The sealing material 50 consists of an insulating material includingfillers 52. In the semiconductor device 140, the thickness t4 of thesecond field plate electrodes 10 is determined in consideration of therelationship with the size of the fillers 52. Other configurations arethe same as those in the first embodiment.

Specifically, in the fourth embodiment, the second field plateelectrodes 10 are configured to be thinner than a predeterminedreference particle diameter of the fillers 52 so as to suppressintrusion of the fillers 52 into inter-electrode gaps occurring betweenthe plural second field plate electrodes 10. The diameter of the fillers52 which are spherical fillers have a certain degree of variation, butfalls into a range from not less than several pun to not more thanseveral tens pun. In this diameter range, the diameters of the fillers52 which may intrude into the gaps between the plural second field plateelectrodes 10 are equal to about several μm. The “predeterminedreference particle diameter” may be calculated based on the particlediameter specification of the fillers 52 as follows. A simple averagevalue of particle diameters of the fillers 52 is referred to as“particle diameter simple average D_(AVE)”, and σ represents a standarddeviation of the particle diameters of the fillers 52. A value obtainedby multiplying σ by a predetermined coefficient k is represented by kσ.The predetermined reference particle diameter is a value obtained bysubtracting kσ from the particle diameter simple average D_(AVE). It ispreferable that the predetermined reference particle diameter is set to“D_(AVE)−3σ” by setting k to 3. The thickness t4 is designed to besmaller than the predetermined reference particle diameter. As a result,even when the fillers 52 having sufficiently smaller than the averageparticle size exist, it is possible to prevent such small diameterfillers 52 from intruding into the inter-electrode gaps.

FIGS. 13 and 14 are diagrams showing comparative examples relating tothe present embodiment. When the second field plate electrodes 10 arethick, a deep inter-electrode gap is formed between the adjacent secondfield plate electrodes 10. Due to the inter-electrode gaps, irregulargaps of the protective insulating film 11 are generated as shown in FIG.13. As shown in FIG. 13, the fillers 52 of the sealing material 50 mayintrude into the irregular gaps of the protective insulating film 11.The fillers 52 intruding into the irregular gaps apply force to thesecond field plate electrodes 10 in a direction indicated by an arrow inFIG. 13, whereby the second field plate electrodes 10 are deformed in adirection parallel to the plane direction of the semiconductor chip 20as schematically shown in FIG. 14.

In this regard, according to the fourth embodiment, the intrusion of thefillers 52 as shown in FIG. 13 can be suppressed by suppressing thethickness t4 of the second field plate electrodes 10 so that thethickness t4 is sufficiently small. As a result, electrode deformationcaused by the fillers 52 can be suppressed.

The fourth embodiment may be modified so that the upper surface of thefirst emitter electrode 8 is lower than the upper surfaces of the secondfield plate electrodes 10. In this case, after the thickness t4 of thesecond field plate electrodes 10 is suppressed, the first emitterelectrode 8 is thinned so that the upper surface of the first emitterelectrode 8 is further lower than the upper surfaces of the second fieldplate electrodes 10. Accordingly, it is preferable that the firstemitter electrode 8 is thinned within a range which is allowable inconsideration of an electric resistance value, etc. required to thefirst emitter electrode 8. In addition, the various modificationsdescribed with reference to the first embodiment may be applied to thefourth embodiment. Also, the fourth embodiment may be modified so thatthe cell surface electrode portion 30 includes the first emitterelectrode 8 and the second emitter electrode 16 as in the case of thesecond embodiment. Furthermore, as in the case of the third embodiment,such a modification that the interlayer insulating film 7 in the cellportion 21 is replaced by the interlayer insulating film 17 as in thecase of the third embodiment may be applied to the fourth embodiment.

Fifth Embodiment

FIG. 15 is a cross-sectional view showing a structure of a semiconductordevice 150 according to a fifth embodiment. The semiconductor device 150is different from the semiconductor device 140 according to the fourthembodiment in that the second field plate electrodes 10 are replaced bysecond field plate electrodes 10 b. In the fourth embodiment, the firstemitter electrode 8 and the second field plate electrodes 10 are formedof the same material, whereas they are formed of different materials inthe fifth embodiment. The configurations other than described above aresimilar to those of the fourth embodiment.

The second field plate electrodes 10 b are formed of a semi-insulatingnitride film. By using the semi-insulating nitride film, corrosion ofthe second field plate electrodes 10 b can be suppressed even whenmoisture infiltrates. As a result, the reliability of the semiconductordevice 150 can be enhanced.

The semiconductor device 150 of the fifth embodiment is the same as thatof the fourth embodiment in the configurations other than the secondfield plate electrodes 10 b. However, the present invention is notlimited to this configuration, and the second field plate electrodes 10of each of the semiconductor devices 100 to 130 described with referenceto the first to third embodiments may be replaced by the second fieldplate electrodes 10 b according to the fifth embodiment.

Sixth Embodiment

FIG. 16 is a cross-sectional view showing a structure of a semiconductordevice 160 according to a sixth embodiment. The semiconductor device 160is different from the semiconductor device 150 according to the fifthembodiment in that the second field plate electrodes 10 are replaced bysecond field plate electrodes 10 c. Furthermore, the semiconductordevice 160 of the sixth embodiment is different from the semiconductordevice 150 according to the fifth embodiment in that the semiconductorchip 20 further includes an inner peripheral boundary portion 24 and atemperature sensing diode 9 c. The configurations other than describedabove are similar to those of the fifth embodiment. The second fieldplate electrodes 10 c are formed of a polysilicon film. According to thesixth embodiment, corrosion of the second field plate electrodes 10 ccan be suppressed.

In the semiconductor device 160, the peripheral edge surface structureportion 32 includes first field plate electrodes 9 b and second fieldplate electrodes 10 c. Like the first field plate electrodes 9 accordingto the first embodiment, the first field plate electrodes 9 b are formedof an n-type first polysilicon film. The second field plate electrodes10 c are formed of a second polysilicon film which is stacked in a stepdifferent from that of the first polysilicon film.

The semiconductor chip 20 includes the inner peripheral boundary portion24 sandwiched between the cell portion 21 and the peripheral edgeportion 22. The temperature sensing diode 9 c is provided on the innerperipheral boundary portion 24. The temperature sensing diode 9 cincludes a first portion 9 c 1 formed of a first polysilicon film and asecond portion 9 c 2 which is doped into a p-type. The temperature ofthe semiconductor chip 20 can be measured by measuring a forward voltageof the temperature sensing diode 9 c.

A part of the second polysilicon film is used to form a gate pad 34, andanother part of the second polysilicon film forms the second field plateelectrodes 10 c. Corrosion of the second field plate electrodes 10 c canbe suppressed by forming the second field plate electrodes 10 c ofpolysilicon. Furthermore, a gate wire having a low resistance can beformed by forming the gate pad 34 of the second polysilicon film.

A first technical idea that the second field plate electrodes 10 c areformed of the second polysilicon film and a second technical idea thatthe temperature sensing diode 9 c is provided at the inner peripheralboundary portion 24 are included in the sixth embodiment. The firsttechnical idea and the second technical idea may be implementedindependently of each other. That is, in the sixth embodiment, the innerperipheral boundary portion 24 and the temperature sensing diode 9 c maybe omitted while the second field plate electrodes 10 c are left.Alternatively, in the sixth embodiment, the second field plateelectrodes 10 c may be replaced by any of the second field plateelectrodes 10 and 10 b while the temperature sensing diode 9 c is leftat the inner peripheral boundary portion 24.

The semiconductor device 160 according to the sixth embodiment is thesame as that of the fifth embodiment in the configurations other thanthe second field plate electrodes 10 c and the inner peripheral boundaryportion 24. However, each of the semiconductor devices 100 to 140described with reference to the first to fourth embodiments may bemodified so as to be provided with the second field plate electrodes 10c and the inner peripheral boundary portion 24 according to the sixthembodiment.

Seventh Embodiment

FIG. 17 is a flowchart showing a method of manufacturing a semiconductordevice according to a seventh embodiment. According to the flowchart ofFIG. 17, the semiconductor device 100 according to the first embodimentcan be manufactured. In the flowchart of FIG. 17, a step of preparing asemiconductor wafer is first executed (step S100). “The front surface ofthe semiconductor wafer” and “the back surface of the semiconductorwafer” in the seventh embodiment correspond to “the front surface of thesemiconductor chip 20” and “the back surface of the semiconductor chip20” in the first embodiment”, respectively after the semiconductor waferis diced.

Next, an element forming step for forming a semiconductor active elementin the cell portion 21 of the semiconductor wafer is executed (stepS102). In this step, plural cell portions 21 are predetermined on thesemiconductor wafer. Since plural semiconductor chips are generallymanufactured from one semiconductor wafer, the plural cell portions 21are set in a single semiconductor wafer so as to be arranged whilespaced apart from one another in the plane direction of onesemiconductor wafer. An element forming process of impurityimplantation, etching, etc. is executed on each of the plural cellportions 21. As a result, as described with reference to FIG. 2, thebase layer 3, the plural trench gates 2, the plural emitter layers 4,and the plural diffusion layers 5 are provided on the surface side ofthe semiconductor wafer. As described with reference to FIG. 2, then-type first buffer layer 12, the n-type second buffer layer 13, and thecollector layer 14 are provided on the back surface side of thesemiconductor wafer. As a result, IGBT is formed in each of the cellportions 21.

Next, the surface structure of the semiconductor wafer is formed (stepS104). Specifically, in this step, the cell surface electrode portion30, the peripheral edge surface structure portion 32 and the gate pad 34described with reference to the first embodiment are formed on thesurface side of the semiconductor wafer. Here, the cell surfaceelectrode portion 30 and the peripheral edge surface structure portion32 are formed so that the front-surface level difference dtf satisfiesthe condition of the expression (2) described with reference to thefirst embodiment.

Next, a back surface grinding step is executed (step S106). In thisstep, thinning of the wafer is performed by grinding the back surface ofthe semiconductor wafer. When the back side of the semiconductor waferis ground, specifically, the surface of the semiconductor wafer is firstprotected with a protective tape or the like. Next, the back surface ofthe semiconductor wafer is ground with a grinder. Irregularities on thesurface of the semiconductor wafer cause variations in grinding depth ofthe back surface of the semiconductor wafer. The irregularitiescorresponding to the front-surface level difference dtf and the endportion front-surface level difference dtdf are transferred onto theback surface of the semiconductor wafer due to the variations ingrinding depth. By this transfer of the irregularities, the firstback-surface level difference dtb and the second back-surface leveldifference dtp are formed on the back surface of the semiconductor waferas shown in FIG. 2 in the first embodiment.

The usefulness of back surface grinding for semiconductor wafers will bedescribed. First, from the viewpoint of energy saving, IGBTs and diodesare used in a field of general-purpose inverters, AC servos or the like.The IGBT and the diode are used for a power module or the like forperforming variable speed control of a three-phase motor or the like. Inorder to reduce inverter losses, devices each having low switching lossand on-voltage are required as IGBTs and diodes. The most part of theon-voltage is the resistance of the thick n-type base layer required tohold the withstand voltage. In order to reduce the resistance of thebase layer, it is effective to thin the semiconductor wafer. Byperforming the back surface grinding step in the above step S106, adevice having low switching loss and low on-resistance can be obtained.

Next, the collector electrode 15 is formed on the whole surface of theback surface of the semiconductor wafer (step S108).

Next, a dicing step is executed (step S110). In this step, thesemiconductor wafer is diced along the dicing line portion 23 providedon the outer periphery of the peripheral edge portion 22. Specifically,dicing is performed on the dicing line portion 23 outside the peripheraledge portion 22 by a dicing blade or the like, whereby the semiconductorchip 20 is cut out from the semiconductor wafer. As a result, thesemiconductor device 100 according to the first embodiment ismanufactured. As the stacked film on the dicing line portion 23 isthinner, the wearing of the dicing blade can be suppressed more greatly.Accordingly, it is desirable not to form an electrode or a film such asthe protective insulating film 11 on the dicing line portion 23. In thisrespect, in the seventh embodiment, as described on the structure of thefirst embodiment, only the interlayer insulating film 7 exists on thedicing line portion 23. Therefore, wearing of the dicing blade can besuppressed in step S110.

Next, a post-processing is executed (step S112). In this step, thesemiconductor device 100 is mounted on a desired product. For example,the semiconductor device 100 may be packaged with a transfer moldingresin material or the like, or may be mounted on a circuit board andaccommodated in a case. The semiconductor device 100 may be used as aswitching element of a power conversion device. Thereafter, the presentmanufacturing flow finishes.

According to the seventh embodiment described above, in step S104, thesurface structure is formed so as to reduce dtf/tc to 1.5% or less,whereby the first back-surface level difference dtb transferred onto theback surface of the semiconductor wafer can be kept within the rangesatisfying the expression (1) of the first embodiment during thegrinding of the back surface of the wafer in step S106. Currentconcentration on the cell portion 21 can be suppressed by suppressingthe level difference to be transferred onto the back surface, so thatthe RBSOA resistance can be improved.

By modifying the manufacturing method according to the seventhembodiment, the semiconductor devices 110 to 150 according to themodification of the first embodiment and the second to fifth embodimentsdescribed above may be manufactured. For example, as a firstmodification of step S104, the second field plate electrodes 10 may beformed to be thinner than the first emitter electrodes 8, therebyforming the semiconductor device 110 shown in FIG. 8. As a secondmodification of step S104, the second emitter electrode 16 may bestacked on the first emitter electrode 8, thereby manufacturing thesemiconductor device 120 shown in FIG. 9. As a third modification ofstep S104, the cell portion interlayer insulating film 17 having a largethickness may be provided on the cell portion 21, thereby manufacturingthe semiconductor device 130 shown in FIG. 10. As a fourth modificationof step S104, the thickness t4 of the second field plate electrodes 10may be determined to be thin in relation to the predetermined referenceparticle diameter of the fillers 52, thereby manufacturing thesemiconductor device 140 shown in FIG. 11. Furthermore, as a fifthmodification of step S104, stacking and patterning of a semi-insulatingnitride film may be performed on the upper layer insulating film 37 toprovide the second field plate electrodes 10 b, whereby thesemiconductor device 150 shown in FIG. 15 is manufactured. Any twomodifications of the foregoing first to fifth modifications may besimultaneously applied to step S104 as long as they do not conflict witheach other.

Eighth Embodiment

FIG. 18 is a flowchart showing a method of manufacturing a semiconductordevice according to an eighth embodiment. In the flowchart of FIG. 18,the step S104 of FIG. 17 is replaced by step S204. Except for thispoint, the eighth embodiment is the same as the seventh embodiment.According to the eighth embodiment, the semiconductor device 160according to the sixth embodiment can be manufactured. FIG. 16 will bereferred to below as needed.

In the flowchart of FIG. 18, the processing of steps S100 and S102 areexecuted as in the case of the flowchart of FIG. 17. Next, formation ofthe temperature sensing diode as well as formation of the surfacestructure is performed (step S204). In step S204, as in the case of stepS104 of the seventh embodiment, IGBT is formed in a pert of the cellportion 21 of the semiconductor wafer, and the cell surface electrodeportion 30 is also formed after the formation of the IGBT. Furthermore,by performing stacking and patterning of the first polysilicon film onthe peripheral edge portion 22, the first field plate electrodes 9 bshown in FIG. 16 are formed. Here, the n-type first polysilicon film isalso provided at the inner peripheral boundary portion 24. Subsequently,a pert of the first polysilicon film provided to the inner peripheralboundary portion 24, located on the side of the peripheral edge portion22, is doped into a p-type, thereby forming the temperature sensingdiode 9 c shown in FIG. 16.

Subsequently, the upper layer insulating film 37 is stacked on the firstfield plate electrodes 9 b. However, the upper layer insulating film 37is not provided on an upper side of the temperature sensing diode 9 c.Stacking and patterning of the second polysilicon film are performed onthe upper layer insulating film 37 in the peripheral edge portion 22,whereby the second field plate electrodes 10 c shown in FIG. 16 areprovided. As a result, the peripheral edge surface structure portion 32is formed.

The second polysilicon film for the second field plate electrodes 10 cis also stacked on “another pert of the cell portion 21” on the surfaceof the semiconductor wafer. The gate pad 34 is formed by the secondpolysilicon film provided in “another part of the cell portion 21”. Thatis, “another part of the cell portion 21” is a part where the gate pad34 shown in plan view of FIG. 1 is formed. According to the above step,there is an advantage that the gate pad 34 and the second field plateelectrodes 10 c are simultaneously formed of the second polysilicon filmstacked in step S204. It is also possible to simplify the process bysimultaneous formation using polysilicon while compatibly performingboth of corrosion suppression of the second field plate electrodes 10 cand reduction of the resistance of control wiring for transmitting acontrol signal.

Thereafter, as in the case of the flowchart of FIG. 17, the steps S106to SI 12 are executed, and the present manufacturing flow finishes. Atleast one of the first to fourth modifications of the above-describedseventh embodiment may be applied to step S204 of the eighth embodiment.

Ninth Embodiment

FIG. 19 is a block diagram showing a power conversion device 200according to a ninth embodiment. In the ninth embodiment, the powerconversion device 200 includes at least one of the semiconductor devices100 to 160 according to the foregoing first to sixth embodiments. Thespecific structure of the power conversion device 200 is not limited toa specific power conversion device. Hereinafter, an application to athree-phase inverter will be exemplified as the ninth embodiment.

FIG. 19 is a block diagram showing a configuration of a power conversionsystem to which the power conversion device 200 according to the ninthembodiment is applied.

The power conversion system shown in FIG. 19 includes a power supply190, the power conversion device 200, and a load 300. The power supply190 is a DC power supply and supplies DC power to the power conversiondevice 200. The power supply 190 can be configured by various types. Thepower supply 190 may be configured by, for example, a DC system, a solarbattery, or a storage battery. The power supply 190 may be constitutedby a rectifier circuit or an AC/DC converter connected to an AC system.Furthermore, the power supply 190 may be constituted by a DC/DCconverter for converting DC power output from a DC system topredetermined electric power.

The power conversion device 200 is a three-phase inverter connectedbetween the power supply 190 and the load 300. The power conversiondevice 200 converts DC power supplied from the power supply 190 into ACpower and supplies AC power to the load 300. As shown in FIG. 19, thepower conversion device 200 includes a main conversion circuit 201, adriving circuit 202, and a control circuit 203. The main conversioncircuit 201 includes plural switching elements 201 a. The mainconversion circuit 201 converts DC power into AC power and outputs theAC power by switching operations of the plural switching elements 201 a.The driving circuit 202 outputs a drive signal for driving each of theswitching elements 201 a. The control circuit 203 outputs a controlsignal for controlling the driving circuit 202 to the driving circuit202.

The load 300 is a three-phase motor driven with AC power supplied fromthe power conversion device 200. The load 300 is not limited to aspecific application. The load 300 is an electric motor to be mounted invarious electric devices. The load 300 may be, for example, an electricmotor used in a hybrid car, an electric car, a rail car, an elevator, oran air conditioner.

Hereinafter, details of the power conversion device 200 will bedescribed. The main conversion circuit 201 includes a switching element201 a and a reflux diode (not shown). The main conversion circuit 201converts the DC power supplied from the power supply 190 into AC powerby the switching operations of the switching elements 201 a, andsupplies the AC power to the load 300.

Various configurations are available as a specific circuit configurationof the main conversion circuit 201. As an example, it is assumed thatthe main conversion circuit 201 according to the ninth embodiment is atwo-level three-phase full-bridge circuit. The two-level three-phasefull-bridge circuit may include six switching elements 201 a and sixreflux diodes (not shown) which are connected in anti-parallel to theswitching elements 201 a, respectively. Any one of the semiconductordevices 100 to 160 according to the first to sixth embodiments describedabove is applied to each of the switching elements 201 a of the mainconversion circuit 201. Respective two switching elements 201 a areconnected in series to constitute upper and lower arms. Each of theupper and lower arms constitutes each phase (U-phase, V-phase, W-phase)of the full-bridge circuit. The output terminals of the upper and lowerarms correspond to three output terminals of the main conversion circuit201, respectively. The three output terminals of the main conversioncircuit 201 are connected to the load 300.

The driving circuit 202 generates a drive signal for driving each of theswitching elements 201 a, and supplies the drive signal to a controlelectrode of each of the switching elements 201 a. The control electrodeof the switching element 201 a is the gate pad 34 of each of thesemiconductor devices 100 to 160 according to the first to sixthembodiments. The driving circuit 202 outputs, to the control electrodeof each switching element 201 a, a drive signal for setting theswitching element 201 a to an ON-state and a drive signal for settingthe switching element 201 a to an OFF-state according to a controlsignal from a control circuit 203 described later. When the switchingelement 201 a is maintained in the ON-state, the drive signal is avoltage signal that is equal to or higher than a threshold voltage ofthe switching element 201 a. When the switching element 201 a ismaintained in the OFF-state, the drive signal is a voltage signal thatis equal to or lower than the threshold voltage of the switching element201 a.

The control circuit 203 controls the switching element 201 a of the mainconversion circuit 201 such that desired power is supplied to the load300. Specifically, a time (ON-time) at which each switching element 201a of the main conversion circuit 201 should be set to the ON-state iscalculated based on power to be supplied to the load 300. For example,the main conversion circuit 201 can be controlled by PWM control formodulating the ON-time of the switching element 201 a according to avoltage to be output. Then, a control command (control signal) isoutputted to the driving circuit 202 so that an ON-signal is output tothe switching element 201 a to be set to the ON-state at each timepoint, and an OFF-signal is output to the switching element 201 a to beset to the OFF-state at each time point. According to the controlsignal, the driving circuit 202 outputs the ON-signal or the OFF-signalas the drive signal to the control electrode of each switching element201 a.

In the power conversion device 200 according to the ninth embodiment,since any one of the semiconductor devices 100 to 160 according to thefirst to sixth embodiments is applied as the switching elements 201 a ofthe main conversion circuit 201, the RBSOA resistance can be secured.

The two-level three-phase inverter is exemplified in the ninthembodiment, but a three-level or multi-level power conversion device maybe used as a modification, or when power is supplied to a single-phaseload, a single-phase inverter may be used. Furthermore, when power issupplied to a DC load or the like, it is also possible to apply to aDC/DC converter or an AC/DC converter.

Furthermore, a system in which the power conversion device 200 is usedis not limited to the system in which the load 300 is an electric motoras described above. The power conversion device 200 may be used as apower supply device for, for example, an electric discharge machine, alaser processing machine, an induction heating cooker, or a contactlesspower supply system. The power conversion device 200 may be used as apower conditioner for a solar power generation system, a power storagesystem or the like.

The features and advantages of the present disclosure (or embodiments)may be summarized as follows. It is possible to keep the difference inthickness between the cell portion and the peripheral edge portionwithin a certain range so that the peripheral edge portion does notbecome excessively thin as compared with the cell portion in thesemiconductor device having a back-surface level difference. Currentconcentration on the cell portion can be suppressed by suppressing theperipheral edge portion from becoming excessively thin as compared withthe cell portion.

Obviously many modifications and variations of the present invention arepossible in the light of the above teachings. It is therefore to beunderstood that within the scope of the appended claims the inventionmay be practiced otherwise than as specifically described.

The entire disclosure of Japanese Patent Application No. 2018-033692,filed on Feb. 27, 2018 including specification, claims, drawings andsummary, on which the Convention priority of the present application isbased, is incorporated herein by reference in its entirety.

The invention claimed is:
 1. A semiconductor device comprising: asemiconductor chip having a plane-body shape having a front surface anda back surface, and including a cell portion including the front surfaceand the back surface and provided in a central region in a plan view ofthe plane-body shape, and a peripheral edge portion including the frontsurface and the back surface and provided around the cell portion in theplan view of the plane-body shape; a cell surface electrode portionprovided on the front surface of the cell portion; and a peripheral edgesurface structure portion that is provided on the front surface of theperipheral edge portion and has a top surface higher than a top surfaceof the cell surface electrode portion, wherein the peripheral edgeportion is made thinner than the cell portion so that the back surfaceof the peripheral edge portion is more concave than the back surface ofthe cell portion, and when a thickness of the cell portion isrepresented by tc and a level difference between the cell portion andthe peripheral edge portion on the back surface is represented by dtb,0%<dtb/tc≤1.5% is satisfied.
 2. The semiconductor device according toclaim 1, wherein the peripheral edge surface structure portion includesa peripheral edge electrode stacked above the front surface of theperipheral edge portion of the semiconductor chip, and a protectiveinsulating film covering the peripheral edge electrode, and theprotective insulating film covers an edge portion of the cell surfaceelectrode portion.
 3. The semiconductor device according to claim 1,wherein the semiconductor chip further includes a dicing line portionprovided on an outer periphery of the peripheral edge portion in theplan view of the plane-body shape, the dicing line portion is madethicker than the peripheral edge portion so that a back surface of thedicing line portion protrudes more than the back surface of theperipheral edge portion, and when a thickness of the dicing line portionis represented by td and a level difference between the dicing lineportion and the peripheral edge portion on the back surface isrepresented by dtp, 1.5%≤dtp/td is satisfied.
 4. The semiconductordevice according to claim 1, wherein the cell surface electrode portionincludes an interlayer insulating film provided on the front surface ofthe cell portion, a contact portion penetrating through the interlayerinsulating film, and a cell electrode that is provided on the interlayerinsulating film and connected to the contact portion, the peripheraledge surface structure portion includes a peripheral edge electrodestacked above the front surface of the peripheral edge portion of thesemiconductor chip, and a protective insulating film covering theperipheral edge electrode, and wherein an upper surface of the cellelectrode is higher than an upper surface of the peripheral edgeelectrode.
 5. The semiconductor device according to claim 1, wherein thecell surface electrode portion includes an interlayer insulating filmprovided on the front surface of the cell portion, a contact portionpenetrating through the interlayer insulating film, a first cellelectrode that is provided on the interlayer insulating film andconnected to the contact portion, and a second cell electrode that isstacked on the first cell electrode and has a thermal resistance lowerthan that of the first cell electrode.
 6. The semiconductor deviceaccording to claim 1, wherein the cell surface electrode portionincludes a cell portion interlayer insulating film provided on the frontsurface of the cell portion, a cell contact portion penetrating throughthe cell portion interlayer insulating film, and a cell electrode thatis provided on the cell portion interlayer insulating film and connectedto the cell contact portion, the peripheral edge surface structureportion includes a peripheral edge portion insulating film providedabove the front surface of the peripheral edge portion, a peripheraledge contact portion penetrating through the peripheral edge portioninsulating film, a peripheral edge electrode that is stacked on theperipheral edge portion insulating film and connected to the peripheraledge contact portion, and a protective insulating film covering theperipheral edge electrode, and wherein the cell portion interlayerinsulating film is made thicker than the peripheral edge portioninsulating film.
 7. The semiconductor device according to claim 1,wherein the peripheral edge surface structure portion includes aplurality of peripheral edge electrodes that are stacked above the frontsurface of the peripheral edge portion and spaced apart from one anotherin a plane direction of the front surface, and a protective insulatingfilm covering the plurality of peripheral edge electrodes, the pluralityof peripheral edge electrodes are made thinner than a predeterminedreference particle diameter of fillers contained in a sealing materialprovided on the peripheral edge surface structure portion, and thepredetermined reference particle diameter is predetermined bysubtracting a multiplication value of a standard deviation of particlediameters of the fillers and a predetermined coefficient from a particlediameter simple average value of the fillers.
 8. The semiconductordevice according to claim 1, wherein the peripheral edge surfacestructure portion includes a peripheral edge electrode provided abovethe front surface of the peripheral edge portion, and the peripheraledge electrode is a semi-insulating nitride film.
 9. The semiconductordevice according to claim 1, wherein the peripheral edge surfacestructure portion includes a peripheral edge electrode provided abovethe front surface of the peripheral edge portion, and the peripheraledge electrode is a polysilicon film.
 10. The semiconductor deviceaccording to claim 1, wherein the semiconductor chip includes an innerperipheral boundary portion sandwiched between the cell portion and theperipheral edge portion, the peripheral edge surface structure portionincludes a first peripheral edge electrode formed of a first polysiliconfilm having a first conductivity type, an interlayer insulating filmstacked on the first peripheral edge electrode, and a second peripheraledge electrode stacked on the interlayer insulating film, and wherein atemperature sensing diode is provided above the inner peripheralboundary portion, and the temperature sensing diode is formed of thefirst polysilicon film and partially doped into a second conductivitytype.
 11. A power conversion device comprising: a main conversioncircuit that includes a semiconductor device, converts input power bythe semiconductor device and outputs the converted input power; adriving circuit for outputting a drive signal for driving thesemiconductor device to the semiconductor device; and a control circuitfor outputting a control signal for controlling the driving circuit tothe driving circuit, wherein the semiconductor device comprises asemiconductor chip having a plane-body shape having a front surface anda back surface, and including a cell portion including the front surfaceand the back surface and provided in a central region in a plan view ofthe plane-body shape, and a peripheral edge portion including the frontsurface and the back surface and provided around the cell portion in theplan view of the plane-body shape, a cell surface electrode portionprovided on the front surface of the cell portion, and a peripheral edgesurface structure portion that is provided on the front surface of theperipheral edge portion and has a top surface higher than a top surfaceof the cell surface electrode portion, the peripheral edge portion ismade thinner than the cell portion so that the back surface of theperipheral edge portion is more concave than the back surface of thecell portion, and when a thickness of the cell portion is represented bytc and a level difference between the cell portion and the peripheraledge portion on the back surface is represented by dtb, 0%<dtb/tc≤1.5%is satisfied.
 12. A semiconductor device manufacturing methodcomprising: a preparing step of preparing a semiconductor wafer having afront surface and a back surface; an element forming step of forming asemiconductor active element in a cell portion as a predetermined partin the semiconductor wafer; a surface structure forming step of forminga cell surface electrode portion on a front surface of the cell portionafter the semiconductor active element is formed, and forming aperipheral edge surface structure portion in a peripheral edge portionaround the cell portion on the front surface of the semiconductor waferso that the peripheral edge surface structure has a top surface higherthan a top surface of the cell surface electrode portion, the cellsurface electrode portion and the peripheral edge surface structureportion being formed so that 0%<dtf/tc≤1.5% is satisfied when athickness of the cell portion is represented by tc and a difference inheight between the top surface of the cell surface electrode portion andthe top surface of the peripheral edge surface structure portion isrepresented by dtf; a back surface grinding step of performing waferthinning of grinding the back surface of the semiconductor wafer afterthe cell surface electrode portion and the peripheral edge surfacestructure portion are formed, whereby a level difference occurring onthe front surface due to the cell surface electrode portion and theperipheral edge surface structure portion is transferred onto the backsurface of the peripheral edge portion; and a dicing step of dicing thesemiconductor wafer along a dicing line provided on an outer peripheryof the peripheral edge portion after performing the wafer thinning. 13.The semiconductor device manufacturing method according to claim 12,wherein the surface structure forming step comprises: a step of formingthe semiconductor active element in a part of the cell portion on thefront surface of the semiconductor wafer; a step of forming a controlelectrode pad connected to a control electrode of the semiconductoractive element at another part of the cell portion on the front surfaceof the semiconductor wafer; and a step of providing the peripheral edgeportion with a first field plate electrode, an interlayer insulatingfilm stacked on the first field plate electrode, and a second fieldplate electrode stacked on the interlayer insulating film, therebyforming the peripheral edge surface structure portion, and wherein thecontrol electrode pad and the second field plate electrode are formed ofpolysilicon stacked in the same step.